Reversible Logic Synthesis Benchmarks Page


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Function 2-to-4 decoder (.pla file) has 3 inputs and 4 outputs. If enable bit (E, one of the 3 inputs) is low, all the output lines will be zero. If the enable bit is high, one of the four output lines will become high selected by the remaining two input lines. This function was proposed by Vishal Gupta from IIT-Madras, India.
 
Picture Machine-readable version Model Garbage Gate count Quantum cost Author(s) Date
here
here
NCTSF
2*
3*
21
V. Gupta
November, 2005
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* - this value is optimal.