Reversible Logic Synthesis Benchmarks Page

    The machine-readable format is a .tfc file which consists of the following strings.

• 1^st string is the list of all variables (lines) participating in the calculation; all entities are deliminated by commas. This string starts with the keyword ".v ".
• 2^nd string is the ordered list of all input variables (lines) for the function to be calculated with the entities deliminated by commas. The beginning of this list is labeled with ".i ".
• 3^rd string is the list of output lines separated by commas; it starts with the control sequence ".o ". Optional string starting with quantifier ".ol" defines the labels for the outputs in the order they appear in the output list. If output labels are not specified, the program will assign the input labels to the corresponding output.
• 4^th string contains values for the input constants in the order they appear on the first string without any spaces. If no input constants are needed, this string is not present. This string starts with ".c ".
• 5^th string, and every non-empty string thereafter, contain either: a) the word "BEGIN" indicating the beginning of a network, b) exactly one gate written in the form described below c) the word "END" indicating the end of the circuit. The file should list the gates in the order they appear in the actual design.
• The circuit file may also include comments, indicated by a "#" symbol in the beginning of a string.

• Toffoli gates are written as "tn ", where "t" indicates Toffoli and "n" is the size of the Toffoli gate (number of variables in it) followed by the list of variables, such that the EXORed variable (target of the gate) is at the end of the list.
• Fredkin gates are written as "fn ", where "f" indicates Fredkin and "n" is the size of the corresponding Fredkin gate followed by the list of variables, such that the SWAPed variables (targets of the gate) are at the end of the list.

Example. A reversible circuit file for 3-bit adder is as follows.